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 | | From: | Bjørn B. Larsen | | Subject: | Re: dram circuits | | Date: | Fri, 12 Nov 2004 15:48:30 +0100 |
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"Adnan Aziz" wrote in message
news:dbf9db48.0411091450.2ce50019@posting.google.com...
> i teach a vlsi design class at UT austin, and there were a couple of
> questions in my last lecture on DRAMs that i couldn't answer.
>
> the text (weste and harris, "cmos vlsi design", 3rd edition, excellent
> book) and my DRAM reference (keeth & baker, dram circuit design)
> werent much help, so i thought i'd ask the net.
>
> - Q1. why is the bitline pre-charged to V_DD/2 (instead of V_DD). i
> thought this would be for performance, i.e., get a larger swing
> quicker, but at least from a simple model, the opposite seems to be
> true. perhaps it's related to power or noise?
>
When you read the bit, you check if the C has any charge or not. Remember
that the C of the bitline is significantly larger than the C of the trench
capacitor.
When you read you may not observe if the bitline chnges to VDD or to GND but
rather which direction it moves. It will not reach VDD neither GND on the
read alone.
When the read is done, the voltage on the trench capacitor is close to
VDD/2. That is why it is a destructive read and you need to rewrite the
contents of the cell.
> - Q2. shouldn't DRAM writes be faster than reads? (the logic being
> that in reads, the bitline is driven by the trench capacitor, but in
> writes the bitlinehas an active driver. perhaps the reason has
> something to do with senseamp logic compensating for the slow read.)
>
As soon as the bitline moves in any direction, the op.amp. will respond. On
a write you must wait til the bitline and trech capacitor are fulle charged
or discharged. (I think that may be the reason.)
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Have a great day!
Bjørn BL.
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