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 | | From: | Mayank Kaushik | | Subject: | SDRAM (MT48LC8M16A2) interfacing problem with AT91RM9200 :-( | | Date: | 22 Jan 2005 12:02:49 -0800 |
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 | Hi,
Im trying to interface two 128Mbit SDRAMs (MT48LC8M16A2) to the
AT91RM9200, but it doesnt seem to be going right. I dont have any sort
of debugging aid xcept the debug unit connected to the serial port of
my PC, thats how i send the program in. The Master Clock is running at
about 60MHz (~16us time period).Heres the program that im loading in to
init the SDRAM:
====================================
void AT91F_InitSDRAM()
{
int i;
int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;
//* Configure PIOC as peripheral (D16/D31)
AT91F_SDRC_CfgPIO();
//* Setup MEMC to support CS1=SDRAM
AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A;
AT91C_BASE_EBI->EBI_CFGR = 0; //Active high DQs
//* Init SDRAM
//Values taken from the SDRAM
Manual:Cols=9,Rows=12,CAS=2,TWR=2,TRC=5,TRP=2,TRCD=2,TRAS=3,TXSR=5
AT91C_BASE_SDRC->SDRC_CR=0x29912955;
//* 1. A NOP is provided //testing only, consider removing
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NOP_CMD;
for(i=0;i<0xFFFFF;i++)
*pSDRAM = 0;
//* 2. A Precharge All command is issued to the SDRAM
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
*pSDRAM = 0;
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
//* 3. Three Auto-refresh commands are provided, the RAM manual asks
for 2, the atmel manual asks for 8
for(i=0;i<2;i++)
*pSDRAM = 0;
//* 4. A mode register cycle is issued to program the SDRAM parameters
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
for(i = 0; i < 100; i++);
*(pSDRAM+0x20) = 0;
//* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
AT91C_BASE_SDRC->SDRC_MR = 0x0;//Burst length=1
*pSDRAM = 0;
//* 5. Write refresh rate into SDRAMC refresh timer COUNT register
AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT& x200);//4096 refresh
cycles every 64ms, ~384, changed to debug
*pSDRAM = 0;
}
===================================================
To test the RAM is ready, i do the following:
===================================================
volatile char *base = (char *)0x20000000;
volatile int *base2 = (int *)0x20000000;
char buf[10];
*base2 = 0xAABBCCDD;
sprintf( buf, "%x\r\n%x\r\n", *base, *(base+1));//printing the last and
second last byte(little endian)
AT91F_DBGU_Printk( buf );
sprintf( buf, "%x\r\n", *(base + 1));//last byte again..see what
happens..
====================================================
Since im testing the code through HyperTerminal, this is what i see:
====================================================
dd
cc
ff
====================================================
and all subsequent accesses to the 4 addresses shows ff (the data lines
are pulled up, thats where the ff is coming, i thnk..)
This happens every time..whatever ive written on the RAM vanishes when
i access it a second time..seems like a problem with the refresh..a
guess, anyone, or a problem with the code??
Thanx in anticipation,
Mayank
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| | From: | Mayank Kaushik | | Subject: | Re: SDRAM (MT48LC8M16A2) interfacing problem with AT91RM9200 :-( | | Date: | 23 Jan 2005 22:11:20 -0800 |
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| Hi Karl,
Ive made some changes to the code..i removed the initial NOP sequence,
it seemed to have no effect..
Code:
int i;
int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;
//* Configure PIOC as peripheral (D16/D31)
AT91F_SDRC_CfgPIO();
//* Setup MEMC to support CS1=SDRAM
AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A;
AT91C_BASE_EBI->EBI_CFGR = 0;
//* Init SDRAM
AT91C_BASE_SDRC->SDRC_CR = 0x29912955;
//* 2. A Precharge All command is issued to the SDRAM
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
*pSDRAM = 0;
//* 3. Eight Auto-refresh are provided
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
for(i=0;i<7;i++)
*pSDRAM = 0;
//* 4. A mode register cycle is issued to program the SDRAM parameters
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
*(pSDRAM+0x80) = 0;
//4.5 Three NOPs to take care of tMRD
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NOP_CMD;
for(i=0; i<2; i++)
*pSDRAM = 0;
//* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
//Normal Mode, 32 bit word length
AT91C_BASE_SDRC->SDRC_MR = 0x0;
*pSDRAM = 0;
//* 5. Write refresh rate into SDRAMC refresh timer COUNT register
AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT & 0x2E0);//4096 refresh
cycles every 64ms
*pSDRAM = 0;
=================================================
this is how im checking the SDRAM:
volatile char *base = (char *)0x20000000;
volatile int *base2 = (int *)0x20000000;
char buf[10];
*base2 = 0xAABBCCDD;
sprintf( buf, "%x\r\n", *(base2));
AT91F_DBGU_Printk( buf );
AT91F_DBGU_Printk( "\r\n=============\r\n" );
sprintf( buf,"\r\n%x\r\n", *(base2));
AT91F_DBGU_Printk( buf );
++++++++++++++++++++++++++++++++++++++
As you can see, im reading the same location twice..to check whether
the RAM is "holding on" to the data;turns out that its not;
++++++++++++++++++++++++++++++++++++++
Output:
aabbccdd
=============
ffffffff
++++++++++++++++++++++++++++++++++++++
The second read of the same location does not find anything..also, if i
put a delay betwee the write and the read, i find nothing!
Code:
++++++++++++++++++++++++++++++++++++++
*base2 = 0xAABBCCDD;
delay();
sprintf( buf, "%x\r\n", *(base2));
AT91F_DBGU_Printk( buf );
++++++++++++++++++++++++++++++++++++++
Output:
ffffffff
++++++++++++++++++++++++++++++++++++++
Looks like a problem with the refresh rate...but ive checked and
rechecked everything! Help!
Thanks in anticipation
Mayank
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| | From: | Mayank Kaushik | | Subject: | Re: SDRAM (MT48LC8M16A2) interfacing problem with AT91RM9200 :-( | | Date: | 23 Jan 2005 22:05:47 -0800 |
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| Hi,
Ive gone through with some changes, this is what the init code for the
SDRAM looks like now:
int i;
int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;
//* Configure PIOC as peripheral (D16/D31)
AT91F_SDRC_CfgPIO();
//* Setup MEMC to support CS1=SDRAM
AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A;
AT91C_BASE_EBI->EBI_CFGR = 0;
//* Init SDRAM
AT91C_BASE_SDRC->SDRC_CR = 0x29912955;
//* 2. A Precharge All command is issued to the SDRAM
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
*pSDRAM = 0;
//* 3. Eight Auto-refresh are provided
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
for(i=0;i<7;i++)
*pSDRAM = 0;
//* 4. A mode register cycle is issued to program the SDRAM parameters
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
*(pSDRAM+0x80) = 0;
//4.5 Three NOPs to take care of tMRD
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NOP_CMD;
for(i=0; i<2; i++)
*pSDRAM = 0;
//* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
//Normal Mode, 32 bit word length
AT91C_BASE_SDRC->SDRC_MR = 0x0;
*pSDRAM = 0;
//* 5. Write refresh rate into SDRAMC refresh timer COUNT register
AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT & 0x2E0);//4096 refresh
cycles every 64ms
*pSDRAM = 0;
=================================================
this is how im checking the SDRAM:
volatile char *base = (char *)0x20000000;
volatile int *base2 = (int *)0x20000000;
char buf[10];
*base2 = 0xAABBCCDD;
sprintf( buf, "%x\r\n", *(base2));
AT91F_DBGU_Printk( buf );
AT91F_DBGU_Printk( "\r\n=============\r\n" );
sprintf( buf,"\r\n%x\r\n", *(base2));
AT91F_DBGU_Printk( buf );
++++++++++++++++++++++++++++++++++++++
As you can see, im reading the same location twice..to check whether
the RAM is "holding on" to the data;turns out that its not;
++++++++++++++++++++++++++++++++++++++
Output:
aabbccdd
=============
ffffffff
++++++++++++++++++++++++++++++++++++++
The second read of the same location does not find anything..also, if i
put a delay betwee the write and the read, i find nothing!
Code:
++++++++++++++++++++++++++++++++++++++
*base2 = 0xAABBCCDD;
delay();
sprintf( buf, "%x\r\n", *(base2));
AT91F_DBGU_Printk( buf );
++++++++++++++++++++++++++++++++++++++
Output:
ffffffff
++++++++++++++++++++++++++++++++++++++
Looks like a problem with the refresh rate...but ive checked and
rechecked everything! Help!
Thanks in anticipation
Mayank
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| | From: | Mayank Kaushik | | Subject: | Re: SDRAM (MT48LC8M16A2) interfacing problem with AT91RM9200 :-( | | Date: | 22 Jan 2005 14:10:53 -0800 |
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| Hi Karl,
Karl Olsen wrote:
> I am also about to bring up a new AT91RM9200 system. I have no
hardware
> yet, so please share your findings. My hardware has one MT48LC8M32
instead
> of your two '8M16, so initialisation should be the same.
sure :-)
> > for(i = 0; i < 100; i++);
> > *(pSDRAM+0x20) = 0;
>
> This looks wrong. Remeber that CPU A2 --> SDRAM A0 etc., so the
address
> should be *(pSDRAM+0x80).
Whoops, ure right..i wasnt paying attention to the datasheet.that
should be 0x80, thanx. Il try that out n see if it works. As of now its
behaving strangely :-S, maybe becoz of this.
Also, the SDRAMC section in the AT91RM9200 manual and the SDRAM
datasheet differ on some points..i guess i should stick to the SDRAM
datasheet.
Wil get results on my Monday, your Sunday
Regards
Mayank
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| | From: | Karl Olsen | | Subject: | Re: SDRAM (MT48LC8M16A2) interfacing problem with AT91RM9200 :-( | | Date: | Sat, 22 Jan 2005 22:38:54 +0100 |
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"Mayank Kaushik" wrote in message
news:1106424169.684320.101510@c13g2000cwb.googlegroups.com...
> Im trying to interface two 128Mbit SDRAMs (MT48LC8M16A2) to the
> AT91RM9200, but it doesnt seem to be going right. I dont have any sort
> of debugging aid xcept the debug unit connected to the serial port of
> my PC, thats how i send the program in. The Master Clock is running at
> about 60MHz (~16us time period).Heres the program that im loading in to
> init the SDRAM:
I am also about to bring up a new AT91RM9200 system. I have no hardware
yet, so please share your findings. My hardware has one MT48LC8M32 instead
of your two '8M16, so initialisation should be the same.
> ====================================
> void AT91F_InitSDRAM()
> {
> int i;
> int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;
>
> //* Configure PIOC as peripheral (D16/D31)
> AT91F_SDRC_CfgPIO();
>
> //* Setup MEMC to support CS1=SDRAM
> AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A;
> AT91C_BASE_EBI->EBI_CFGR = 0; //Active high DQs
>
> //* Init SDRAM
>
>
> //Values taken from the SDRAM
> Manual:Cols=9,Rows=12,CAS=2,TWR=2,TRC=5,TRP=2,TRCD=2,TRAS=3,TXSR=5
>
> AT91C_BASE_SDRC->SDRC_CR=0x29912955;
I haven't checked your hex, but I am using the same parameters.
> //* 1. A NOP is provided //testing only, consider removing
>
> AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NOP_CMD;
> for(i=0;i<0xFFFFF;i++)
> *pSDRAM = 0;
SDCK should be stable and NOPs or INHIBITs issued for at least 100 usec
before the precharge, so you might not want to remove this completely.
> //* 2. A Precharge All command is issued to the SDRAM
> AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
> *pSDRAM = 0;
>
> AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
> //* 3. Three Auto-refresh commands are provided, the RAM manual asks
> for 2, the atmel manual asks for 8
> for(i=0;i<2;i++)
> *pSDRAM = 0;
>
> //* 4. A mode register cycle is issued to program the SDRAM parameters
> AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
> for(i = 0; i < 100; i++);
> *(pSDRAM+0x20) = 0;
This looks wrong. Remeber that CPU A2 --> SDRAM A0 etc., so the address
should be *(pSDRAM+0x80).
> //* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
> AT91C_BASE_SDRC->SDRC_MR = 0x0;//Burst length=1
> *pSDRAM = 0;
This is your first real access to SDRAM, and it should happen at least three
clocks after the mode register programming. This delay is probably not
guaranteed by the _MODE_LMR_CMD mode, so you may want to issue three NOPs
after the mode programming.
> //* 5. Write refresh rate into SDRAMC refresh timer COUNT register
> AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT& x200);//4096 refresh
> cycles every 64ms, ~384, changed to debug
> *pSDRAM = 0;
>
> }
> ===================================================
> To test the RAM is ready, i do the following:
> ===================================================
> volatile char *base = (char *)0x20000000;
> volatile int *base2 = (int *)0x20000000;
> char buf[10];
>
> *base2 = 0xAABBCCDD;
>
> sprintf( buf, "%x\r\n%x\r\n", *base, *(base+1));//printing the last and
> second last byte(little endian)
>
> AT91F_DBGU_Printk( buf );
> sprintf( buf, "%x\r\n", *(base + 1));//last byte again..see what
> happens..
> ====================================================
> Since im testing the code through HyperTerminal, this is what i see:
> ====================================================
> dd
> cc
> ff
> ====================================================
> and all subsequent accesses to the 4 addresses shows ff (the data lines
> are pulled up, thats where the ff is coming, i thnk..)
> This happens every time..whatever ive written on the RAM vanishes when
> i access it a second time..seems like a problem with the refresh..a
> guess, anyone, or a problem with the code??
Regards,
Karl Olsen
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