 | | From: | Saurav Malla | | Subject: | Benchmarking an ARMulator model | | Date: | 30 Dec 2004 00:32:07 -0800 |
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 | Thanks for the reply.
Caches are enabled, that can be verified from the debuggers output
window where it says that there is 16 kb data and instruction cache.
And for the memory wait states, currently i have used the default
memory model with zero wait states.
can you tell me that is it alright to get such variance in speed in
the simulated H/W model and the actual H/W? Does that mean that the
ARMulator model cannot simulate realtime operation?
waiting for a reply.
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| | From: | William Munns | | Subject: | Re: Benchmarking an ARMulator model | | Date: | 30 Dec 2004 09:20:42 GMT |
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| armSavvy@gmail.com (Saurav Malla) wrote in
news:beca3ee0.0412300032.5c2416b4@posting.google.com:
> Thanks for the reply.
>
> Caches are enabled, that can be verified from the debuggers
> output window where it says that there is 16 kb data and
> instruction cache. And for the memory wait states,
> currently i have used the default memory model with zero
> wait states.
That just tells you there are caches on the core, not that they
are enabled (for the ARMUlator a tick in the 'Default
Pagetables' box does this)
IIRC for the 926 the default memory system has 3 wait states
> can you tell me that is it alright to get such variance in
> speed in the simulated H/W model and the actual H/W? Does
> that mean that the ARMulator model cannot simulate realtime
> operation?
>
> waiting for a reply.
You appear to have missed the second part of the answer
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